Title :
Suppression of delay time instability on frequency using field shield isolation technology for deep sub-micron SOI circuits
Author :
Maeda, S. ; Yamaguchi, Y. ; Kim, I.-J. ; Iwamatsu, T. ; Ipposhi, T. ; Miyamoto, S. ; Maegawa, S. ; Ueda, K. ; Nii, K. ; Mashiko, K. ; Inoue, Y. ; Miyoshi, H.
Author_Institution :
ULSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan
Abstract :
It was demonstrated that Field Shield (FS) isolation technology can suppress the delay time instability depending on operating frequency. FS isolation technology has been proposed to tie the body potential without any area penalties in gate array. Moreover, the effect of body resistance on the instability was also investigated using device simulation.
Keywords :
MOS logic circuits; VLSI; circuit analysis computing; circuit stability; delays; digital simulation; isolation technology; logic arrays; silicon-on-insulator; body potential; body resistance; deep sub-micron SOI circuits; delay time instability; device simulation; field shield isolation technology; gate array; operating frequency; Circuit simulation; Circuit testing; Delay effects; Electrodes; Frequency; Immune system; Isolation technology; Laboratories; MOS devices; MOSFET circuits;
Conference_Titel :
Electron Devices Meeting, 1996. IEDM '96., International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-3393-4
DOI :
10.1109/IEDM.1996.553138
