Self calibrated pipelined analog-to-digital converter for video rate applications

Author

Nassar, I.M. ; Khalil, A.H. ; Salama, A.E.

Author_Institution

Fac. of Eng., Cairo Univ., Giza, Egypt

fYear

2004

fDate

16-18 March 2004

Lastpage

42377

Abstract

This paper concerns the design and simulation of a 10 bits video rate pipelined analog-to-digital converter. A self calibration mechanism is proposed for compensating any errors caused by tolerance of capacitors, which is common in CMOS analog circuits. A 1.5 bits per stage architecture is chosen and digital correction on the binary output is performed. A switched capacitor circuit is used as the main stage with offset compensation where necessary. Simulation is performed using a CMOS 0.8μm technology model. At a sampling rate of 6.75MSPS, an INL and a DNL of 13.5LSB and 16 LSB were achieved, respectively.

Keywords

CMOS analogue integrated circuits; analogue-digital conversion; error compensation; signal sampling; switched capacitor networks; 0.8 microns; CMOS analog circuits; digital correction; error compensation; offset compensation; pipelined analog-to-digital converter; sampling rate; self calibration mechanism; switched capacitor circuit; video rate applications; Analog circuits; Analog-digital conversion; CMOS analog integrated circuits; CMOS technology; Calibration; Circuit simulation; Design engineering; Frequency; Semiconductor device modeling; Switched capacitor circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Science Conference, 2004. NRSC 2004. Proceedings of the Twenty-First National

Print_ISBN

977-5031-77-X

Type

conf

DOI

10.1109/NRSC.2004.1321763

Filename

1321763