An 11-Gb/s Receiver With a Dynamic Linear Equalizer in a 22-nm CMOS

Author

Sumesaglam, Taner

Author_Institution

Intel, Folsom, CA, USA

Volume

61

Issue

4

fYear

2014

fDate

Apr-14

Firstpage

219

Lastpage

223

Abstract

A receiver circuit employing a dynamic linear equalization technique is presented. The new circuit method removes the traditional continuous-time linear equalizer (CTLE) and builds equalization into strong-arm latches (SALs). Fabricated in a 22-nm CMOS technology, the receiver´s performance is experimentally verified at 11 Gb/s with better than bit error rate 10^-12 at 0.17 mW/Gb/s power efficiency, which advances the state of the art. The power efficiency is 55% better than the CTLE alternative on the same silicon. Analysis and simulation methods for the dynamic linear equalization and other architectural details are also presented.

Keywords

CMOS logic circuits; equalisers; flip-flops; receivers; CMOS technology; CTLE; SAL; bit error rate; bit rate 11 Gbit/s; continuous-time linear equalizer; dynamic linear equalization technique; efficiency 55 percent; receiver circuit; size 22 nm; strong-arm latches; Bit error rate; CMOS integrated circuits; Clocks; Equalizers; Integrated circuit modeling; Receivers; Transient analysis; Analog front end; CMOS; Graphics Double Data Rate (GDDR); analog integrated circuits; dynamic linear equalizer; equalization; high-speed I/O; memory interface; receiver; single-ended;

fLanguage

English

Journal_Title

Circuits and Systems II: Express Briefs, IEEE Transactions on

Publisher

ieee

ISSN

1549-7747

Type

jour

DOI

10.1109/TCSII.2014.2305217

Filename

6747955