ANN accelerator by parallel processor based on DSP

Author

Onuki, Jun ; Maenosono, Taka-aki ; Shibata, Masakazu ; Iijima, Nobukazu ; Mitsui, Hideo ; Yoshida, Yukio ; Sone, Mototaka

Author_Institution

Dept. of Electr. & Electron. Eng., Musashi Inst. of Technol., Tokyo, Japan

Volume

2

fYear

1993

fDate

25-29 Oct. 1993

Firstpage

1913

Abstract

Artificial neural networks (ANN) become popular in various fields, especially in the pattern recognition. In the recognition stage of ANN the time that is required is very short but in the learning stage it becomes long according to the number of learning data and ANNs scale. This is a serious problem in the case of simulating ANN by an emulation software or a small-size emulation system. So a super computer or general purpose computer is generally needed for pursuing these simulations. A high speed parallel processor was realized by using digital signal processors (DSP) which is effective to high speed data processing. This parallel processor realized a ANN that has three layers architecture with the backpropagation learning algorithm (BP method) at high speed.

Keywords

backpropagation; digital signal processing chips; feedforward neural nets; neural net architecture; parallel architectures; parallel processing; backpropagation learning algorithm; data processing; digital signal processors; hypercube; neural networks; parallel processor; three layers architecture; Artificial neural networks; Backpropagation; Computational modeling; Computer architecture; Computer simulation; Data processing; Digital signal processing; Digital signal processors; Emulation; Pattern recognition;

fLanguage

English

Publisher

ieee

Conference_Titel

Neural Networks, 1993. IJCNN '93-Nagoya. Proceedings of 1993 International Joint Conference on

Print_ISBN

0-7803-1421-2

Type

conf

DOI

10.1109/IJCNN.1993.717029

Filename

717029