SEU-Hardened Energy Recovery Pipelined Interconnects for On-Chip Networks

Pipelined on-chip interconnects are used in on-chip networks to increase the throughput of interconnects and to achieve freedom in choosing arbitrary network topologies. Since reliability and energy consumption are prominent issues in on-chip networks, they should be carefully considered in the design of pipelined interconnects. In this paper, we propose the use of energy recovery techniques to construct low energy and reliable pipelined on-chip interconnects. The proposed designs have been evaluated using detailed SPICE simulations. In the reliability analysis, the SEU fault model is considered as it is a major reliability concern in the sequential circuits (pipelining memory elements) implemented in DSM technologies. The experimental studies show that the proposed energy recovery designs can be used to reduce the energy consumption by about 30% while provide a better reliability (comparable to what is achievable from fault tolerance techniques) as compared to conventional pipelined interconnects.