Title :
Low Power and Reliable Interconnection with Self-Corrected Green Coding Scheme for Network-on-Chip
Author :
Huang, Po-Tsang ; Fang, Wei-Li ; Wang, Yin-Ling ; Hwang, Wei
Author_Institution :
Nat. Chiao-Tung Univ., Hsinchu
Abstract :
In this paper, a low power joint bus and error correction coding is proposed to provide reliable and energy- efficient interconnection for network-on-chip (NoC) in nano- scale technology. The proposed self-corrected ";green"; (low power) coding scheme is constructed by two stages, which are triplication error correction coding (ECC) stage and green bus coding stage. Triplication ECC provides a more reliable mechanism to advanced technologies. Moreover, in view of lower latency of decoder, it has rapid correction ability to reduce the physical transfer unit size of switch fabrics by self- corrected technique in bit level. The green bus coding employs more energy reduction by a joint triplication bus power model for crosstalk avoidance. In addition, the circuitry of green bus coding is more simple and effective. Based on UMC 90 nm CMOS technology, the simulation results show self-corrected green coding can achieve 34.4% energy reduction with small codec overhead. This approach not only makes the NoC applications tolerant against transient malfunctions, but also realizes energy efficiency.
Keywords :
error correction codes; integrated circuit interconnections; network-on-chip; error correction coding; green bus coding stage; low power joint bus; network-on-chip; reliable interconnection; self- corrected green coding scheme; CMOS technology; Crosstalk; Decoding; Delay; Error correction codes; Fabrics; Integrated circuit interconnections; Network-on-a-chip; Semiconductor device modeling; Switches; interconnnection; low power; network-on-chip; reliability;
Conference_Titel :
Networks-on-Chip, 2008. NoCS 2008. Second ACM/IEEE International Symposium on
Conference_Location :
Newcastle upon Tyne
Print_ISBN :
0-7695-3098-2
DOI :
10.1109/NOCS.2008.4492727