A novel multiphase clock generator based on digital DLL designed for oversampling in transceiver

This paper describes a novel multiphase clock generator with simplicity, short locking time and low jitter performance. The multiphase clock generator is based on digital delay-locked loop (DLL). The novel digital DLL incorporates lead-lag phase detector and digital controlled delay line (DCDL) with a simple counter to generate equally spaced five-phase clocks. The whole circuit has been simulated by using Cadence´s SPECTRE software and TSMC´s library of 0.25 μn CMOS model. The worst peak-to-peak long-term jitter of the multiphase clocks is less than 23ps at 480MHz. And the locking time is about several clock cycles. It can be perfectly applied in circuit of USB for oversampling in high speed transceiver.