Title :
Delta-Sigma ADC for Ternary Code System (Part II: Decimation Filter Realization)
Author :
Korotkov, A.S. ; Morozov, D.V. ; Sinha, Amitabha
Author_Institution :
St. Petersburg State Polytech. Univ., St. Petersburg
Abstract :
This paper is sequential of [1]. Realization and simulation of a decimation FIR filter of an analog-to-digital converter for ternary code signal processing are presented. Description and simulation results of a ternary D flip-flop, a ternary full adder, and the FIR filter in a whole are given.
Keywords :
FIR filters; adders; delta-sigma modulation; flip-flops; ternary codes; FIR filter; delta-sigma analog-to-digital converter; ternary D flip-flop; ternary code system; Adders; Analog-digital conversion; Circuits; Clocks; Digital filters; Equations; Finite impulse response filter; Flip-flops; Inverters; Switches;
Conference_Titel :
Signals, Circuits and Systems, 2007. ISSCS 2007. International Symposium on
Conference_Location :
Iasi
Print_ISBN :
1-4244-0969-1
Electronic_ISBN :
1-4244-0969-1
DOI :
10.1109/ISSCS.2007.4292654
