Title :
Lp Based Cell Selection With Constraints Of Timing, Area, And Power Consumption
Author :
Tamiya, Y. ; Matsunaga, Yusuke
Keywords :
CMOS logic circuits; Clocks; Delay effects; Energy consumption; Laboratories; Large scale integration; Libraries; Time factors; Timing; Tuned circuits;
Conference_Titel :
Computer-Aided Design, 1994., IEEE/ACM International Conference on
Print_ISBN :
0-8186-3010-8
DOI :
10.1109/ICCAD.1994.629822
