Title :
32-bit RISC CPU Based on MIPS-Instruction Decoder Module Design
Author :
Yi, Kui ; Ding, Yue-Hua
Author_Institution :
Dept. of Comput. Sci. & Inf. Eng., WuHan Polytech. Univ., Wuhan, China
Abstract :
In this paper, through analysis of function and working theory of RISC CPU instruction decoder module, we design instruction decoder module of 32-bit CPU. The instruction decoder includes register file, write back data to register file, sign bit extend, relativity check, and it is simulated on QuartusII successfully.
Keywords :
instruction sets; microprocessor chips; reduced instruction set computing; 32-bit RISC CPU; MIPS; RISC microprocessor; function analysis; instruction decoder module design; instruction set; million instruction per second; reduced instruction set computing; register file; relativity check; sign bit extend; Computer science; Decoding; Design engineering; Field programmable gate arrays; Hardware design languages; Information analysis; Open source software; Pipelines; Reduced instruction set computing; Registers; Data Flow; Data Path; MIPS; Pipeline;
Conference_Titel :
Web Mining and Web-based Application, 2009. WMWA '09. Second Pacific-Asia Conference on
Conference_Location :
Wuhan
Print_ISBN :
978-0-7695-3646-0
DOI :
10.1109/WMWA.2009.62
