Fast prototyping of a DSP core

This paper describes the UTS-DSP (University of Tehran and SAMA Research Center) IC design process. Using CISC architecture, UTS-DSP has an efficient pipeline to cover a complete instruction set as a high-performance DSP processor. This paper has mainly focused on major parts of UTS-DSP design process, modeling and verification as a fast and efficient process to design DSP cores. Modeling of the UTS-DSP is done by VHDL hardware description language and then synthesized for test implementation via FPGAs. A dedicated hardware has been developed for FPGA implementation with 250,000 logic gates and over five million memory bits.