Adiabatic circuits for low power logic

Adiabatic logic circuits offer significant reductions in power dissipation when compared with standard static CMOS design. However, many implementation issues remain to be solved. This paper will discuss low power design and then focus on adiabatic logic circuits and the required power clock needed to drive them. A new power clock is presented which does not utilize any external components and provides the gradual rise, hold, and fall times required for adiabatic logic.