Title :
Adiabatic circuits for low power logic
Author :
Akers, L.A. ; Suram, R.
Author_Institution :
Dept. of Electr. & Comput. Eng., Missouri Univ., Columbia, MO, USA
Abstract :
Adiabatic logic circuits offer significant reductions in power dissipation when compared with standard static CMOS design. However, many implementation issues remain to be solved. This paper will discuss low power design and then focus on adiabatic logic circuits and the required power clock needed to drive them. A new power clock is presented which does not utilize any external components and provides the gradual rise, hold, and fall times required for adiabatic logic.
Keywords :
CMOS logic circuits; clocks; logic design; low-power electronics; CMOS chip; adiabatic logic circuit; low-power design; power clock; power dissipation; CMOS logic circuits; CMOS technology; Capacitance; Clocks; Computer architecture; Energy consumption; Logic circuits; Power dissipation; Power generation; Voltage;
Conference_Titel :
Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on
Print_ISBN :
0-7803-7523-8
DOI :
10.1109/MWSCAS.2002.1186854
