Title :
Scalability of MSD memory effect
Author :
Hubert, A. ; Cristoloveanu, S. ; Bawedin, M. ; Ernst, T.
Author_Institution :
CEA-LETI, MINATEC, Grenoble
Abstract :
The scaling requirements of bulk DRAMs have lead to various concepts of capacitor-less single-transistor (1T) DRAM. Amongst them, the MSDRAM, a double-gate Fully Depleted SOI transistor, exhibits attractive performance resulting from the MSD hysteresis effect. Systematic measurements are presented showing the impact of transistor parameters on the MSD effect. It is found that MSD is maintained for small dimensions even in standard SOI MOSFETs without specific optimization.
Keywords :
DRAM chips; MOSFET; silicon-on-insulator; MSD hysteresis effect; MSD memory effect; capacitor-less single-transistor DRAM; double-gate fully depleted SOI transistor; metastable dip effect; transistor parameters; Capacitors; Hysteresis; MOSFETs; Metastasis; Random access memory; Scalability; Semiconductor films; Silicon; Threshold voltage; Tunneling;
Conference_Titel :
Ultimate Integration of Silicon, 2009. ULIS 2009. 10th International Conference on
Conference_Location :
Aachen
Print_ISBN :
978-1-4244-3704-7
DOI :
10.1109/ULIS.2009.4897557
