A 5 MHz silicon CMOS hierarchical boost DC-DC converter design using macromodels for a 1U process

Author

Hooper, Mark S. ; Hall, Jeff W. ; Kenny, Steve

Author_Institution

Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA

Volume

2

fYear

2002

fDate

4-7 Aug. 2002

Abstract

This work presents an innovative design of a high frequency and potentially highly efficient boost DC-DC converter with an input voltage of 2.7-3.3 V and with a programmable output voltage of 4-9 V. Current sourcing capability is between 40 mA-360 mA. A low power boost DC-DC converter designed in CMOS which partially uses circuit macromodels-designed and tested using Cadence tools-for an all CMOS silicon process illustrates this design. The key features of this design are very high switching frequency, reconfigurability, silicon all CMOS implementation, and mixed signal simulation capability. The boost converter has a simulation switching frequency of 5 MHz, an average efficiency of 50% and an output ripple voltage of about 30 mV.

Keywords

CMOS integrated circuits; circuit CAD; circuit simulation; elemental semiconductors; integrated circuit design; integrated circuit modelling; low-power electronics; silicon; switching convertors; 1U process; 2.7 to 3.3 V; 4 to 9 V; 40 to 360 mA; 5 MHz; 50 percent; Cadence tools; Si; Si CMOS DC-DC converter design; circuit macromodels; hierarchical boost DC-DC converter; high switching frequency; low power converter; macromodels; mixed signal simulation capability; reconfigurability; CMOS process; Circuit simulation; Circuit testing; DC-DC power converters; Frequency conversion; Process design; Signal design; Silicon; Switching frequency; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on

Print_ISBN

0-7803-7523-8

Type

conf

DOI

10.1109/MWSCAS.2002.1186870

Filename

1186870