DocumentCode
3292549
Title
Scalability of advanced partially depleted n-MOSFET devices on biaxial strained SOI substrates
Author
Flachowsky, S. ; Höntschel, J. ; Wei, A. ; Illgen, R. ; Hermann, P. ; Herrmann, T. ; Klix, W. ; Stenzel, R. ; Ramirez, A. ; Horstmann, M. ; Kernevez, N. ; Cayrefourcq, I. ; Metral, F. ; Kennard, M. ; Guiot, E.
Author_Institution
Dept. of Electr. Eng., Univ. of Appl. Sci. Dresden, Dresden
fYear
2009
fDate
18-20 March 2009
Firstpage
161
Lastpage
164
Abstract
Biaxial tensile strained substrates offer strong electron mobility enhancements resulting in large drive current gains. For short channel n-MOSFETs, however, these improvements diminish. Root causes for this performance degradation are investigated through experiments and simulations. Elastic stress relaxation arising from shallow trench isolation (STI) is found to be negligible for current state-of-the-art transistors. On the other hand, parasitic source/drain resistance seems to be responsible for the limitation of drain current gains in deeply scaled devices. This effect is even further aggravated by an increased parasitic source/drain resistance in sSOI devices compared to standard SOI.
Keywords
MOSFET; electron mobility; isolation technology; semiconductor device models; silicon-on-insulator; stress relaxation; biaxial strained SOI substrates; elastic stress relaxation; electron mobility; partially depleted n-MOSFET devices; scalability; shallow trench isolation; short channel n-MOSFET; source/drain resistance; Degradation; Electron mobility; MOSFET circuits; Region 1; Scalability; Silicon on insulator technology; Strain measurement; Surface resistance; Tensile strain; Tensile stress;
fLanguage
English
Publisher
ieee
Conference_Titel
Ultimate Integration of Silicon, 2009. ULIS 2009. 10th International Conference on
Conference_Location
Aachen
Print_ISBN
978-1-4244-3704-7
Type
conf
DOI
10.1109/ULIS.2009.4897562
Filename
4897562
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