Static noise margin analysis of double-gate MOSFETs SRAM

A continuous, analytic model of double-gate MOSFETs is used to simulate all transistors in a six-transistor (6T) SRAM cell. The static noise margin (SNM) of 6T-SRAM cells is investigated as a function of supply voltage, threshold voltage, temperature effects, and the size of transistors. The worst case of reduction in SNM due to threshold voltage fluctuation is investigated by making the two inverters in a SRAM cell exactly mismatched. Results show that enlarging the width of pull-down transistors can improve SNM and expand the minimum nominal threshold voltage before SNM vanishes. Besides, enlarging the nominal threshold voltage of access-transistors also helps SNM and makes SRAM cells tolerable to severer threshold voltage fluctuation.