Title :
Novel self-limiting program scheme utilizing N-channel select transistors in P-channel DINOR flash memory
Author :
Ohnakado, T. ; Takada, H. ; Hayashi, K. ; Sugahara, K. ; Satoh, S. ; Abe, H.
Author_Institution :
Adv. Technol. R&D Center, Mitsubishi Electr. Corp., Hyogo, Japan
Abstract :
This paper describes a novel self-limiting program scheme applying N-channel select transistors in the P-channel DINOR flash memory, which makes it possible to maintain the high programming throughput even for future lower-voltage flash memories. Using this scheme, programming stops automatically at the desired threshold voltage state without any conventional verify operations. Moreover, the width of the additional applied pulses is a very short 0.1 /spl mu/s and therefore it hardly degrades the programming speed at all. This novel scheme is expected to become a key technology for realization of the future, high-performance, lower-supply-voltage P-channel DINOR flash memory.
Keywords :
EPROM; MOS memory circuits; PLD programming; parallel programming; 0.1 mus; N-channel select transistors; P-channel DINOR flash memory; high programming throughput; lower-voltage flash memories; programming speed; self-limiting program scheme; Automatic programming; Degradation; Fault location; Flash memory; Leakage current; Research and development; Space vector pulse width modulation; Threshold voltage; Throughput; Transistors;
Conference_Titel :
Electron Devices Meeting, 1996. IEDM '96., International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-3393-4
DOI :
10.1109/IEDM.1996.553149