Title :
Watermark induced High Density Via failures in sub micron CMOS fabrication
Author :
Chew, Alex ; Au Hh ; Han Sh ; Neo, T.L. ; Tan, Jackson ; Chai Kw ; Chua, Samuel
Author_Institution :
Syst. on Silicon Manuf. Co. Pte. Ltd., Singapore
Abstract :
High via resistance was detected in the high density via structure in our 0.15 mum BEOL (Back-End-Of-Line) yield monitoring test vehicle. A localized insulating layer was found on top of plug in test vehicle causing high via resistance. The failure was attributed to watermark induced contaminants on top of the W plug. It was shown that the failure could be avoided by eliminating watermark formation on the wafer in the post CMP cleaning process.
Keywords :
CMOS integrated circuits; chemical mechanical polishing; insulating materials; integrated circuit testing; integrated circuit yield; watermarking; CMP cleaning process; IC technology; back-end-of-line yield monitoring test vehicle; localized insulating layer; size 0.15 mum; sub micron CMOS fabrication; watermark induced contaminants; watermark induced high density; Cleaning; Fabrication; Gold; Oxidation; Plugs; Silicon; Slurries; Testing; Vehicles; Watermarking;
Conference_Titel :
Semiconductor Manufacturing, 2006. ISSM 2006. IEEE International Symposium on
Conference_Location :
Tokyo
Print_ISBN :
978-4-9904138-0-4
DOI :
10.1109/ISSM.2006.4493007
