Low power and high speed explicit-pulsed flip-flops

Author

Zhao, Peiyi ; Darwish, Tarek ; Bayoumi, Magdy

Author_Institution

Center for Adv. Comput. Studies, Louisiana Univ., Lafayette, LA, USA

Volume

2

fYear

2002

fDate

4-7 Aug. 2002

Abstract

Flip-flops play an important role in building digital CMOS designs. Their design and optimization is critical for high-performance and low power systems. In this paper, we propose high-performance and low power flip-flops based on the explicit-pulsed flip-flop (EPFF). These new flip-flops eliminate the hazardous glitches associated with the original EPFF output. The Static-EPFF (SEPFF) is developed for low-power dissipation purposes; it reduces the power dissipation by 13.9%-15.7%, and it enhances the speed by 4.86%-7.87%. For high-speed objectives, the dual path single-transistor-clocked EPFF (STC-EPFF) achieves 21% enhancement in speed over EPFF at the expense of increased power dissipation (12%).

Keywords

CMOS logic circuits; circuit optimisation; flip-flops; low-power electronics; digital CMOS designs; dual path single-transistor-clocked EPFF; explicit-pulsed flip-flops; low power systems; optimization; power dissipation; Buildings; CMOS technology; Circuit noise; Clocks; Delay; Design optimization; Flip-flops; Noise generators; Power dissipation; Power systems;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on

Print_ISBN

0-7803-7523-8

Type

conf

DOI

10.1109/MWSCAS.2002.1186902

Filename

1186902