Collector depletion region investigation of SOI SiGe HBTs

A growing interest is focused on HBT integrating with SOI CMOS in smaller scale. So IBM proposes a vertical structure of SiGe HBT. This paper proposes and analyses the space charge region, the field and depletion width model of the folded collector. The results indicate, the space charge region consists of intrinsic junction depletion and MOS capacitance depletion, the width of the space charge region increases with larger doping concentration of the collector, larger reverse junction voltage, and smaller substrate voltage, the region features a vertical expansion followed by a lateral expansion. This paper provides valuable reference to the SiGe nun-wave BiCMOS circuit design and simulation on thin film SOI.