DocumentCode :
3293101
Title :
Order Reduction by Explicit Moment Matching Based on State Variable Approach
Author :
Dumitriu, Lucia ; Iordache, Mihai
Author_Institution :
"Politehnica" Univ. of Bucharest, Bucharest
Volume :
2
fYear :
2007
fDate :
13-14 July 2007
Firstpage :
1
Lastpage :
4
Abstract :
The paper presents a sistematic procedure for order reduction needed in an efficient analog large-scale circuit simulation. The procedure uses a reduced number of the original circuit moments to obtain an accurate approximation of the circuit function corresponding to an equivalent reduced-size circuit. An efficient program for state equation formulation and transfer function generation allow the computation of the original circuit moments. Some examples are done to illustrate the method.
Keywords :
circuit simulation; equivalent circuits; integrated circuit modelling; transfer functions; analog large-scale circuit simulation; circuit function approximation; circuit moments; equivalent reduced-size circuit; explicit moment matching; order reduction; state equation formulation; state variable approach; transfer function generation; Analog circuits; Analog computers; Circuit simulation; Circuit testing; Equations; Equivalent circuits; Geometry; Large-scale systems; Transfer functions; Vectors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signals, Circuits and Systems, 2007. ISSCS 2007. International Symposium on
Conference_Location :
Iasi
Print_ISBN :
1-4244-0969-1
Electronic_ISBN :
1-4244-0969-1
Type :
conf
DOI :
10.1109/ISSCS.2007.4292774
Filename :
4292774
Link To Document :
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