Title :
Internal chip ESD phenomena beyond the protection circuit
Author :
Duvvury, C. ; Rountree, R.N. ; Adams, O.
Author_Institution :
Texas Instrum. Inc., Dallas, TX, USA
Abstract :
VDD-VSS protection design considerations to meet MIL-STD requirements are discussed. Internal chip electrostatic-discharge (ESD) damage due to direct stress applied between VDD and VSS pins is illustrated, and possible solutions are discussed. It is shown that induced current paths can exist when outputs/inputs are stressed with respect to VDD or VSS stress, and if the internal layout is not carefully considered, the overall protection level can degrade. An unusual internal ESD phenomenon that was observed for I/O pins stressed with respect to VDD is reported. The results show that there exists a window of threshold voltages where the I/O protection is not effective due to interaction with the internal chip layout
Keywords :
CMOS integrated circuits; circuit reliability; discharges (electric); electrostatics; integrated circuit technology; protection; CMOS IC; I/O pins; MIL-STD requirements; VDD-VSS protection design; electrostatic-discharge; induced current paths; internal chip ESD damage; internal layout; protection circuit; threshold voltages; CMOS technology; Circuit optimization; Circuit testing; Circuits; Degradation; Electrostatic discharge; Instruments; Internal stresses; Pins; Protection; Threshold voltage; Variable structure systems;
Conference_Titel :
Reliability Physics Symposium 1988. 26th Annual Proceedings., International
Conference_Location :
Monterey, CA
DOI :
10.1109/RELPHY.1988.23419
