Internal chip ESD phenomena beyond the protection circuit

Author

Duvvury, C. ; Rountree, R.N. ; Adams, O.

Author_Institution

Texas Instrum. Inc., Dallas, TX, USA

fYear

1988

fDate

12-14 Apr 1988

Firstpage

19

Lastpage

25

Abstract

V_DD-V_SS protection design considerations to meet MIL-STD requirements are discussed. Internal chip electrostatic-discharge (ESD) damage due to direct stress applied between V_DD and V_SS pins is illustrated, and possible solutions are discussed. It is shown that induced current paths can exist when outputs/inputs are stressed with respect to V_DD or V_SS stress, and if the internal layout is not carefully considered, the overall protection level can degrade. An unusual internal ESD phenomenon that was observed for I/O pins stressed with respect to V_DD is reported. The results show that there exists a window of threshold voltages where the I/O protection is not effective due to interaction with the internal chip layout

Keywords

CMOS integrated circuits; circuit reliability; discharges (electric); electrostatics; integrated circuit technology; protection; CMOS IC; I/O pins; MIL-STD requirements; V_DD-V_SS protection design; electrostatic-discharge; induced current paths; internal chip ESD damage; internal layout; protection circuit; threshold voltages; CMOS technology; Circuit optimization; Circuit testing; Circuits; Degradation; Electrostatic discharge; Instruments; Internal stresses; Pins; Protection; Threshold voltage; Variable structure systems;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium 1988. 26th Annual Proceedings., International

Conference_Location

Monterey, CA

Type

conf

DOI

10.1109/RELPHY.1988.23419

Filename

23419