A novel structure of silicon field emission cathode with sputtered TiW for gate electrode

A novel techniques for a gated silicon field emission cathode is proposed in order to decrease the spacing between tip and gate electrode of the device, leading to low voltage operation. This technique is based on the penetration of the sputtered Ti_0.1W_0.9 for the gate electrode into the shadowed area surrounding the tip with good step coverage, and is completely compatible to the conventional 1.2 μm CMOS standard processes. The experimental results indicate that the gate hole diameter is greatly reduced to sub-half micron (~0.4 μm) from the initial mask size (~1.2 μm), and I-V characteristics of the cathodes show low turn-on voltages (~25 V) in ultrahigh vacuum (<3.0×10^-7 Torr) and the good linearity of Fowler-Nordheim plots