Title :
Layout Verification For Submicron CMOS Cell Libraries To Improve ESD/latchup Reliability
Author :
Ker, Ming-Dou ; Hsiao, Sue-Mei ; Lin, Jiann-Homg
Keywords :
CMOS technology; Circuit testing; Electrostatic discharge; Internal stresses; Libraries; Pins; Protection; System testing; Variable structure systems; Voltage;
Conference_Titel :
VLSI Technology, Systems, and Applications, 1997. Proceedings of Technical Papers. 1997 International Symposium on
Conference_Location :
Taipei, Taiwan
Print_ISBN :
0-7803-4131-7
DOI :
10.1109/VTSA.1997.614930
