Title :
An FPGA implementation of the floating point addition
Author :
Souani, Chokri ; Abid, Mohamed ; Tourki, Rached
Author_Institution :
Fac. of Sci., Electron. & Micro-Electron. Lab., Monastir, Tunisia
fDate :
31 Aug-4 Sep 1998
Abstract :
Recent algorithms require a great number of arithmetic operations. Some algorithms require adequate precision imposing, the use of a long register for arithmetic operators. In this paper, the authors present a floating point format and its FPGA implementation for the addition operation. This format is different from the IEEE standard format, but is able to satisfy a sufficiently large dynamic of operators with an appropriate precision
Keywords :
field programmable gate arrays; floating point arithmetic; FPGA implementation; arithmetic operations; arithmetic operators; computation precision; floating point addition; floating point format; operators dynamic; Degradation; Dynamic range; Field programmable gate arrays; Floating-point arithmetic; Hardware; Laboratories; Propagation delay; Quantization; Robustness; Very large scale integration;
Conference_Titel :
Industrial Electronics Society, 1998. IECON '98. Proceedings of the 24th Annual Conference of the IEEE
Conference_Location :
Aachen
Print_ISBN :
0-7803-4503-7
DOI :
10.1109/IECON.1998.722915
