Timing optimization for testable convergent tree adders

Author

Huang, Johnnie A. ; Chen, Chien-In Henry ; Romera, Joaquin B.

Author_Institution

LSI Logic Corp., Milpitas, CA, USA

fYear

1998

fDate

13-16 Sep 1998

Firstpage

245

Lastpage

249

Abstract

Carry lookahead adders have been, over the years, an integral part of microprocessor architecture. Structures and levels of adders vary depending on the carry output. In this paper, analysis and optimization processes are first performed on a testable convergent tree adder. It is shown that the structure of the tree provides for a high fanout with an imbalanced tree structure which contributes to a racing effect and increases the timing delay of the circuit. The timing optimization is then realized by reducing the maximum fanout of the adder and by balancing the tree circuit. For a 56-b testable tree adder the optimization in 1.2 μm CMOS produces a 6.37% increase in speed of the critical path while only losing 2.16% in area. The full testability of the circuit is maintained in the optimized adder design

Keywords

CMOS logic circuits; adders; carry logic; circuit optimisation; design for testability; integrated circuit design; integrated circuit testing; logic design; logic testing; timing; 1.2 micron; CMOS process; DFT; adder testability; carry lookahead adders; imbalanced tree structure; maximum fanout reduction; optimized adder design; testable convergent tree adders; timing optimization; tree circuit balancing; Adders; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Integrated circuit interconnections; Large scale integration; Logic arrays; Logic testing; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference 1998. Proceedings. Eleventh Annual IEEE International

Conference_Location

Rochester, NY

ISSN

1063-0988

Print_ISBN

0-7803-4980-6

Type

conf

DOI

10.1109/ASIC.1998.722982

Filename

722982