Title :
Increased Fab Efficiency through the use of Small Lot Size FOUPs
Author :
Buice, Carl U. ; Bonora, Tony
Author_Institution :
Asyst Technol., Fremont
Abstract :
Frequently large foundry fabs are running 10 or fewer wafers in standard 25 wafer FOUPs. The reasons for running lots that are significantly smaller than the full capacity vary from Fab to Fab and lot to lot. This paper investigates benefits and drawbacks of running small lot sizes and proposes alternate solutions to using partially filled 25 wafer FOUPs.
Keywords :
integrated circuits; lot sizing; fab efficiency; foundry fabs; front opening unified pods; small lot size; Costs; Foundries; Investments; Manufacturing processes; Production facilities; Throughput;
Conference_Titel :
Semiconductor Manufacturing, 2006. ISSM 2006. IEEE International Symposium on
Conference_Location :
Tokyo
Print_ISBN :
978-4-9904138-0-4
DOI :
10.1109/ISSM.2006.4493069
