Title :
Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT´99)
Abstract :
The following topics were dealt with: yield; testing techniques; BIST architectures; fault modeling and simulation; design for testing; self-checking processing units and systems; self-checking memories and interconnections; diagnosis; reconfiguration
Keywords :
VLSI; built-in self test; design for testability; fault diagnosis; fault simulation; fault tolerance; integrated circuit testing; integrated circuit yield; integrated memory circuits; logic testing; reconfigurable architectures; BIST architectures; VLSI systems; defect tolerance; design for testing; diagnosis; fault modeling; fault simulation; fault tolerance; interconnections; reconfiguration; self-checking memories; self-checking processing units; testing techniques; yield;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 1999. DFT '99. International Symposium on
Conference_Location :
Albuquerque, NM, USA
Print_ISBN :
0-7695-0325-x
DOI :
10.1109/DFTVS.1999.802862
