The application of 2-D logarithms to low-power hearing-aid processors

Author

Li, H. ; Muscedere, R. ; Jullien, G.A. ; Dimitrv, V.S.

Author_Institution

VLSI Res. Group, Windsor Univ., Ont., Canada

Volume

3

fYear

2002

fDate

4-7 Aug. 2002

Abstract

This paper discusses the application of a new two-dimensional logarithmic number system (2DLNS) to the design of low-power processors for hearing-aid applications. The paper concentrates on the architecture of an optimized second base 8-band filterbank and an associated 16-bit binary to 2DLNS converter. The processor takes advantage of the low complexity, orthogonal nature, of the arithmetic used for multiplication and compression, and a simple binary converter. Details are provided for the filterbank processor including the description of a 0.18μm CMOS test chip recently submitted for fabrication.

Keywords

CMOS digital integrated circuits; biomedical electronics; data compression; digital signal processing chips; hearing aids; low-power electronics; 0.18 micron; 16 bit; 16-bit binary to 2DLNS converter; 2-D logarithms; 2DLNS; CMOS test chip; binary converter; compression; filterbank processor; hearing-aid processors; low-power processors; multiplication; optimized second base 8-band filterbank; Arithmetic; Auditory system; Deafness; Dynamic range; Filter bank; Finite impulse response filter; Frequency; Laboratories; Process design; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on

Print_ISBN

0-7803-7523-8

Type

conf

DOI

10.1109/MWSCAS.2002.1186958

Filename

1186958