Title :
A low power scheduling methodology under the timing constraints
Author_Institution :
North China Univ. of Technol., Beijing, China
Abstract :
In this paper, an E-D-search-based algorithm is proposed to minimize power consumption with resources operating at multiple voltages under the timing constraints. The inputs to the algorithm consist of a data flow graph (DFG) representation of a circuit, the timing constraints, and a design library with fully characterized resources. Experimental results with a number of DSP benchmarks show that the algorithm can achieve significant power reduction.
Keywords :
digital integrated circuits; digital signal processing chips; integrated circuit design; low-power electronics; system-on-chip; DSP benchmarks; E-D-search-based algorithm; digital integrated circuit designs; power consumption minimization; power scheduling methodology; system-on-chip designs; timing constraints; Data flow computing; Delay; Digital integrated circuits; Educational institutions; Energy consumption; Flow graphs; Scheduling algorithm; Time factors; Timing; Voltage;
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits, 2009. IPFA 2009. 16th IEEE International Symposium on the
Conference_Location :
Suzhou, Jiangsu
Print_ISBN :
978-1-4244-3911-9
Electronic_ISBN :
1946-1542
DOI :
10.1109/IPFA.2009.5232618
