Failure analysis of EOS damage case study

Author

Zhang, Qun ; Peng, Grace ; Gao, Xia ; Hamilton, Craig

Author_Institution

Texas Instrum. Semicond. Technol. (Shanghai) Co.Ltd., Shanghai, China

fYear

2009

fDate

6-10 July 2009

Firstpage

373

Lastpage

376

Abstract

Nowadays, with the development of silicon fabrication technology from 130 um technology in early 70´s till present 45 nm technology, the geometries of transistors shrink smaller and smaller, IC devices become more sensitive to electrostatic discharge, or electrical overstress, i.e. ESD/EOS. ESD/EOS, therefore, is one of the major causes of device failures in the semiconductor industry. Tremendous efforts are being made by both component/system level design and IC supplier / EMS/ OEM manufactory control. Failure analysis plays its unique role to validate ESD/EOS failure mechanism and drive the mitigation of ESD/EOS failures. In this paper, real case was stated to show the contribution of our FA results for ATE test program & IC circuit design debugging.

Keywords

electrostatic discharge; failure analysis; integrated circuit design; integrated circuit reliability; integrated circuit testing; nanoelectronics; silicon; ATE test program; EMS-OEM manufactory control; ESD-EOS failure mechanism; IC circuit design debugging; Si; electrical overstress; electrostatic discharge; failure analysis; semiconductor industry; silicon fabrication technology; size 45 nm; system level design; Circuit testing; Earth Observing System; Electronics industry; Electrostatic discharge; Fabrication; Failure analysis; Geometry; Silicon; System-level design; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Physical and Failure Analysis of Integrated Circuits, 2009. IPFA 2009. 16th IEEE International Symposium on the

Conference_Location

Suzhou, Jiangsu

ISSN

1946-1542

Print_ISBN

978-1-4244-3911-9

Electronic_ISBN

1946-1542

Type

conf

DOI

10.1109/IPFA.2009.5232630

Filename

5232630