DocumentCode
3294424
Title
Stratified testing of multichip module systems under uneven known-good-yield
Author
Park, N. ; Lombardi, F.
Author_Institution
Oklahoma State Univ., Stillwater, OK, USA
fYear
1999
fDate
36465
Firstpage
192
Lastpage
200
Abstract
In this paper, a stratified technique is proposed for testing multichip module (MCM) systems. Its advantages are an improvement in quality level (QL) and cost-effectiveness. The proposed testing approach is accomplished in the presence of uneven known-good-yield (KGY) for MCMs consisting of different sets (or strata) of chips. This approach referred to as the lowest yield-stratum first-testing (LYSFT) considers the unevenness of KGY between strata for testing the chips and improving the QL. For comparison purposes, exhaustive testing (ET), random testing (RT) and random stratified testing (RST) are also evaluated. Given the strata, KGY and the sample size of the chips under test, the proposed LYSFT approach allocates and tests the sampled chips in a greedy (first) fashion, while RT and RST select the chip (for RT) and the stratum (for RST) randomly. A Markov-chain model is developed to analyze these testing approaches and is solved analytically in O(SN3) for the LYSFT (where S is the number of strata and N is the number of chips in the MCM). A cost model is proposed as figure of merit and shown to relate the defect level (DL) with the number of tests performed. Parametric results show that the LYSFT dramatically outperforms RT and RST for improving the QL. A considerable reduction in tests can be achieved by the LYSFT at a very small loss in QL compared with ET
Keywords
Markov processes; integrated circuit testing; integrated circuit yield; multichip modules; MCM systems; Markov-chain model; cost model; cost-effectiveness improvement; defect level; exhaustive testing; figure of merit; lowest yield-stratum first-testing; multichip module systems; quality level improvement; random testing; stratified testing; uneven known-good-yield; Computer science; Costs; Fabrication; Manufacturing; Multichip modules; Performance evaluation; Procurement; System testing; Test pattern generators; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI Systems, 1999. DFT '99. International Symposium on
Conference_Location
Albuquerque, NM
ISSN
1550-5774
Print_ISBN
0-7695-0325-x
Type
conf
DOI
10.1109/DFTVS.1999.802885
Filename
802885
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