Title :
Low-power Testing For C-testable Iterative Logic Arrays
Author :
Hwang, Shih-Am ; Wu, Cheng-Wen
Keywords :
CMOS logic circuits; Circuit faults; Circuit testing; Costs; Energy consumption; Logic arrays; Logic testing; Polynomials; Power dissipation; Switching circuits;
Conference_Titel :
VLSI Technology, Systems, and Applications, 1997. Proceedings of Technical Papers. 1997 International Symposium on
Conference_Location :
Taipei, Taiwan
Print_ISBN :
0-7803-4131-7
DOI :
10.1109/VTSA.1997.614934
