Reliability evaluation of power VDMOSFET

Author

Bai, Yun-Xia ; Guo, Chun-Sheng ; Feng, Shi-Wei ; Ding, Kai-Kai ; Zhuang, Si-Xiang ; Su, Rong

Author_Institution

Sch. of Electron. Inf. & Control Eng., Beijing Univ. of Technol., Beijing, China

fYear

2009

fDate

6-10 July 2009

Firstpage

344

Lastpage

347

Abstract

The specific application of power devices has imposed the requirement for intensive investigation of their reliability. In this paper we have investigated the reliability and failure mechanism of power VDMOS. In constant-stress accelerated life test, the three different temperatures (150degC, 165degC and 180degC) are imposed on the devices. Under the bias VDS=7.5V, IDS=0.8A, and the channel temperature T=117degC, the average lifetime is 3.67times10⁶ h , the activation energy E is 0.54eV, and the main failure mechanism is gate damage.

Keywords

MOS integrated circuits; power MOSFET; semiconductor device reliability; constant-stress accelerated life test; current 0.8 A; electron volt energy 0.54 eV; failure mechanism; power VDMOSFET; reliability evaluation; temperature 117 degC; temperature 150 degC; temperature 165 degC; temperature 180 degC; voltage 7.5 V; Acceleration; Degradation; FETs; Failure analysis; Integral equations; Life estimation; Life testing; Power semiconductor switches; Stress; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

Physical and Failure Analysis of Integrated Circuits, 2009. IPFA 2009. 16th IEEE International Symposium on the

Conference_Location

Suzhou, Jiangsu

ISSN

1946-1542

Print_ISBN

978-1-4244-3911-9

Electronic_ISBN

1946-1542

Type

conf

DOI

10.1109/IPFA.2009.5232635

Filename

5232635