A structural approach for space compaction for sequential circuits

Author

Seuring, M. ; Gössel, M.

Author_Institution

Inst. of Comput. Sci., Univ. of Potsdam, Germany

fYear

1999

fDate

36465

Firstpage

227

Lastpage

235

Abstract

In this paper a new structural method for linear output space compaction for synchronous sequential circuits is presented. Based on simple estimates for the probabilities of the existence of sensitized paths from the signal lines to the circuit outputs, optimal output partitions are determined without fault simulation. The method is developed for concurrent checking, but as the experimental results show, it is also effectively applicable in pseudo-random test mode

Keywords

VLSI; design for testability; integrated circuit design; integrated circuit testing; integrated logic circuits; logic design; logic testing; probability; sequential circuits; concurrent checking; error propagation; linear output space compaction; optimal output partitions; probabilities; pseudo-random test mode; sensitized paths; sequential circuits; structural method; synchronous circuits; Bismuth; Compaction; Sequential circuits; Variable speed drives;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 1999. DFT '99. International Symposium on

Conference_Location

Albuquerque, NM

ISSN

1550-5774

Print_ISBN

0-7695-0325-x

Type

conf

DOI

10.1109/DFTVS.1999.802889

Filename

802889

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3294526