A synthesis methodology aimed at improving the quality of TSC devices

Author

Bolchini, C. ; Pomante, L. ; Salice, F. ; Sciuto, D.

Author_Institution

Dip. di Elettronica e Inf., Politecnico di Milano, Italy

fYear

1999

fDate

36465

Firstpage

247

Lastpage

255

Abstract

This paper proposes a synthesis methodology aimed at improving the concurrent error property of combinational TSC devices. The methodology is based on an iterative application of a structural modification of the device (observability modification) and an evaluation of the impact of such a modification. The quality evaluation is performed by means of a cost function for totally self-checking combinational devices which takes into account different aspects besides the area overhead criterion for comparing different realization strategies. The methodology has been validated on a set of MCNC91 benchmarks

Keywords

combinational circuits; fault diagnosis; integrated circuit reliability; iterative methods; logic CAD; MCNC91 benchmarks; combinational TSC devices; concurrent error property; cost function; iterative application; observability modification; quality evaluation; realization strategies; structural modification; synthesis methodology; totally self-checking combinational devices; Built-in self-test; Circuit faults; Circuit synthesis; Circuit testing; Decision support systems; Electrical fault detection; Encoding; Fault detection; Minimization; VHF circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 1999. DFT '99. International Symposium on

Conference_Location

Albuquerque, NM

ISSN

1550-5774

Print_ISBN

0-7695-0325-x

Type

conf

DOI

10.1109/DFTVS.1999.802891

Filename

802891