• DocumentCode
    3294870
  • Title

    Application of passive voltage contrast fault isolation on 65nm SRAM single bit failure

  • Author

    Yang, May ; Liang, Sanan ; Wu, Linfeng ; Lai, Lilung ; Su, Jie ; Niou, Chomg ; Wen, Yoyo ; Zhu, Yvonne

  • Author_Institution
    Semicond. Manuf. Int. Corp., Beijing, China
  • fYear
    2009
  • fDate
    6-10 July 2009
  • Firstpage
    256
  • Lastpage
    259
  • Abstract
    Application of passive voltage contrast at low kV is well-known methodology to identify fault location. In this paper, PVC with high-energy beam instead of at low kV has been performed to one 65 nm technology case and successfully reveals PMOS contact open. The phenomenon and modelling will be further discussed.
  • Keywords
    MOS digital integrated circuits; SRAM chips; PMOS contact; SRAM single bit failure; passive voltage contrast fault isolation; size 65 nm; Circuit simulation; Crosstalk; Distributed parameter circuits; Integrated circuit interconnections; Power transmission lines; Radio frequency; Random access memory; Scattering parameters; Transmission line theory; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Physical and Failure Analysis of Integrated Circuits, 2009. IPFA 2009. 16th IEEE International Symposium on the
  • Conference_Location
    Suzhou, Jiangsu
  • ISSN
    1946-1542
  • Print_ISBN
    978-1-4244-3911-9
  • Electronic_ISBN
    1946-1542
  • Type

    conf

  • DOI
    10.1109/IPFA.2009.5232655
  • Filename
    5232655
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3294870