• DocumentCode
    3295068
  • Title

    Rapidly reconfigurable coarse-grained FPGA architecture for digital filtering applications

  • Author

    Chin, Shu-Shin ; Wu, Wei ; Hong, Sangjin

  • Author_Institution
    Dept. of Electr. & Comput. Eng., State Univ. of New York, Stony Brook, NY, USA
  • Volume
    3
  • fYear
    2002
  • fDate
    4-7 Aug. 2002
  • Abstract
    This paper presents a rapid reconfigurable coarse-grained FPGA architecture targeted for FIR filter, LMS adaptive FIR filters with multiple correlation and FFT/IFFT for digital filtering applications. The proposed architecture can configure up to four pipelined radix-4 or radix-2 2048 point FFT/IFFT, two 32-tap LMS filters or two 64-tap multiple FIR filters. By reducing unnecessary switching of general purpose routing resources, used extensively in fine-grained FPGAs, our approach can achieve the flexibility of a fine-grained FPGA with the performance and area efficiency similar to that of an ASIC.
  • Keywords
    FIR filters; adaptive filters; digital filters; fast Fourier transforms; field programmable gate arrays; least mean squares methods; linear phase filters; logic design; pipeline processing; FFT; IFFT; LMS adaptive FIR filters; coarse-grained FPGA architecture; digital filtering applications; multiple correlation; pipelined radix-2 FFT/IFFT; pipelined radix-4 FFT/IFFT; rapidly reconfigurable FPGA architecture; Adaptive filters; Application software; Application specific integrated circuits; Computer architecture; Digital filters; Field programmable gate arrays; Filtering; Finite impulse response filter; Least squares approximation; Parallel processing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on
  • Print_ISBN
    0-7803-7523-8
  • Type

    conf

  • DOI
    10.1109/MWSCAS.2002.1187006
  • Filename
    1187006