Title :
A wafer scale integration neural network utilizing completely digital circuits
Author :
Yasunaga, Moritoshi ; Masuda, Noboru ; Asai, Mitsauo ; Yamada, Minoru ; Masaki, Akira ; Hirai, Yuzo
Author_Institution :
Hitachi Ltd., Tokyo, Japan
Abstract :
A wafer scale integration (WSI) neural network utilizing completely digital circuits is reported. Three new technologies are used: (1) time-sharing digital bus; (2) efficient utilization of weight storage; and (3) redundant learning control circuit. Items 1 and 2 enable more than 500 neurons and effectively more than 30000 synapses to be fabricated on a 5-in silicon wafer. Item 3 enables a very high yield to be realized on one silicon wafer using a 0.8 mu m CMOS process.<>
Keywords :
CMOS integrated circuits; VLSI; learning systems; microprocessor chips; neural nets; parallel architectures; redundancy; 0.8 micron; CMOS process; Si wafer; WSI; digital circuits; neural network; neurons; redundant learning control circuit; synapses; time-sharing digital bus; wafer scale integration; weight storage; CMOS integrated circuits; Learning systems; Microprocessors; Neural networks; Parallel architectures; Redundancy; Very-large-scale integration;
Conference_Titel :
Neural Networks, 1989. IJCNN., International Joint Conference on
Conference_Location :
Washington, DC, USA
DOI :
10.1109/IJCNN.1989.118701
