Author :
Oechsner, R. ; Frickinger, J. ; Pfeffer, M. ; Schellenberger, M. ; Roeder, G. ; Pfitzner, L. ; Ryssel, H. ; Fritzsche, M. ; Kaushik, V. ; Renaud, D. ; Danel, A. ; Claeys, C. ; Bearda, T. ; Lering, M. ; Graef, M. ; Murphy, B. ; Walther, H. ; Hury, S.
Abstract :
This paper describes the objectives and results of a joint European project named flying wafer. The goal of the project was to provide a methodology for interlinking European R&D centers in micro- and nanotechnologies to a distributed 300 mm CMOS R&D line. The project was carried out as a feasibility study. Therefore, the results provide a model and concept which has the potential of guaranteeing a safe and fast exchange of wafers and data between European R&D nodes to allow multi-site processing. An implementation phase is planed in a second step.
Keywords :
CMOS integrated circuits; nanotechnology; CMOS; flying wafer; microtechnologies; multisite processing; nanotechnologies; CMOS technology; Contamination; Costs; Electron devices; Logistics; Manufacturing industries; Microelectronics; Research and development; Semiconductor device manufacture; Semiconductor device modeling;
