Abstract :
As the development of deep sub-micron (DSM) technique, integration of more communication applications and processing modules in one single chip is becoming feasible. MP-Soc, as an advacned SoC, has strong abilities in processing, software-hardware cooperation. It is widely used in many applications. The development of MP-SoC is far behind the present technology and technique. The bottleneck of MP-SoC is the low communication efficiency of resouces based on bus architecture. The paper studies NoC, the newest communication technology on chip. Summarizes the present studies, points out some key directions in NoC study, with detailed analysis, and designs an experimental platform system for NoC simulation, specificly for MP-SoC. The paper originates from a NoC project, which is supported by National Natural Science Foundation of China
Keywords :
integrated circuit design; network-on-chip; DSM; MP-SoC; National Natural Science Foundation; bus architecture; deep submicron technique; key communication technology; multiprocessor system-on-chip; network-on-chip; software-hardware cooperation; Communication networks; Communications technology; Control systems; Delay effects; Design optimization; Energy consumption; Hardware; Network-on-a-chip; Silicon; Very large scale integration;
