DocumentCode :
3295274
Title :
Best test pattern failure analysis flow for functional logic failure localization by IR-OBIRCH technique
Author :
Machouat, Aziz ; Haller, G. ; Goubier, V. ; Lewis, D. ; Perdu, P. ; Pouget, V. ; Essely, F.
Author_Institution :
STMicroelectronics, Rousset, France
fYear :
2009
fDate :
6-10 July 2009
Firstpage :
191
Lastpage :
194
Abstract :
The optical IR-OBIRCh technique is a standard failure analysis tool used to localize defects that are located at interconnects layers levels. For a functional logic failure, a failing test pattern is used to condition the device into a particular logic state to generate the failure. Commonly, the defect is detected for a set of test patterns. All test patterns will not provide the same IR-OBIRCh response. A random selection of test patterns may not lead to localize the defect by IR-OBIRCh technique or give fake results. We have performed an extended study of IR-OBIRCh response of a functional logic failure in function of test patterns. Based on these results a best test pattern failure analysis flow has been developed and implemented in order to localize a functional logic failure with IR-OBIRCh technique.
Keywords :
automatic test pattern generation; failure analysis; semiconductor device reliability; transistors; best test pattern failure analysis; defect localization; functional logic failure localization; interconnects layers levels; optical IR-OBIRCh technique; Automatic test pattern generation; Failure analysis; Image motion analysis; Laboratories; Logic devices; Logic testing; Optical interconnections; Pattern matching; Performance evaluation; Test pattern generators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits, 2009. IPFA 2009. 16th IEEE International Symposium on the
Conference_Location :
Suzhou, Jiangsu
ISSN :
1946-1542
Print_ISBN :
978-1-4244-3911-9
Electronic_ISBN :
1946-1542
Type :
conf
DOI :
10.1109/IPFA.2009.5232672
Filename :
5232672
Link To Document :
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