• DocumentCode
    3295718
  • Title

    Logic failure analysis 65/45nm device using RCI & nano scale probe

  • Author

    Cho, S.J. ; Kim, T.E. ; Hong, J.K. ; Hong, J.T. ; Kim, H.S. ; Han, Y.W. ; Kwon, S.D. ; Oh, Y.S.

  • Author_Institution
    Failure Anal. Group, Samsung Electron. Co. Ltd. Semicond. Bus., Yongin, South Korea
  • fYear
    2009
  • fDate
    6-10 July 2009
  • Firstpage
    50
  • Lastpage
    53
  • Abstract
    Scan chain failure analysis is more difficult and complicated compared to memory analysis and analysis of defect monitoring test element group (DTEG) which has a large area is also difficult. This paper has verified that various defects of logic process sub 65nm device are easily analyzed through Resistive Contrast Imaging (RCI) and nanoprobe. In addition, Metal5 (M5) bridge defect (Short case) was detected in failure of scan ATPG (Automatic Test Pattern Generation) which has long failing nets and by discovering Via4 (V4) open defect (Open case) by Unetch, it was confirmed that it is possible to analyze high resistance Via failure. And it was verified that position of Cu line void of metal7 (M7) can be localized at high level metal layer. It is judged that it will be used usefully in failure analysis sub 65nm in the future as a technique utilizing principle of RCI and nanoprobe and also it will make lots of contributions to improvement of yield.
  • Keywords
    automatic test pattern generation; electronic engineering computing; failure analysis; logic circuits; ATPG; Metal5; RCI; Via4 open defect; automatic test pattern generation; bridge defect; defect monitoring test element group; high level metal layer; logic failure analysis; metal7; nanoscale probe; resistive contrast imaging; scan chain failure analysis; size 65 nm; Automatic test pattern generation; Bridges; Condition monitoring; Failure analysis; Image analysis; Logic devices; Nanoscale devices; Pattern analysis; Probes; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Physical and Failure Analysis of Integrated Circuits, 2009. IPFA 2009. 16th IEEE International Symposium on the
  • Conference_Location
    Suzhou, Jiangsu
  • ISSN
    1946-1542
  • Print_ISBN
    978-1-4244-3911-9
  • Electronic_ISBN
    1946-1542
  • Type

    conf

  • DOI
    10.1109/IPFA.2009.5232699
  • Filename
    5232699