An overview of physical analysis of nanosize conductive path in ultrathin SiON and high-к gate dielectrics in nanoelectronic devices

Dielectric breakdown in advanced gate stacks in state-of-the-art Si nanoelectronic devices has been one of the key front-end reliability concerns for further CMOS technology downscaling. In this paper, we present the latest findings in using physical analysis techniques such as transmission electron microscopy (TEM)/electron energy loss spectroscopy (EELS)/energy dispersive X-ray spectroscopy (EDS), scanning tunneling microscopy (STM) and ballistic-electron-emission microscopy (BEEM) to study the morphology and chemical nature of nanosize structural defects formed in the dielectrics across the different phases of the overall degradation process. The correlation study between the localized physical changes in the material associated with a breakdown path and the electrical characteristics of the device in the post-BD regime is realized by the ultimate resolving power of the high resolution nanoscale physical characterization tools. Various physical defects associated with the trap generation, percolation path formation and post-breakdown wear-out of the dielectric material are identified and studied. The influence and extent of the different types of defects that are responsible for various unique gate current leakage signatures such as random telegraphic noise (RTN), digital-to-analog breakdown transition, switching of percolation conduction and ultrafast transient failure owing to filamentation are reviewed. The implications of the physical studies on the feasibility of advanced high-κ metal gate stacks are also addressed.