• DocumentCode
    3295848
  • Title

    Hexagonal minimum Steiner tree construction for Y architecture: A case of non-Manhattan routing

  • Author

    Ghosal, P. ; Biswas, Arijit

  • Author_Institution
    Bengal Eng. & Sci. Univ., Shibpur, India
  • fYear
    2012
  • fDate
    5-7 Dec. 2012
  • Firstpage
    160
  • Lastpage
    166
  • Abstract
    Construction of cost-effective global routing trees is one of the primary keys in today´s interconnect centric VLSI layout design under DSM (deep sub-micron) regime. In order to reduce the interconnect delay, traditional Manhattan (M-) routing architectures are currently being replaced by the diagonal X architectures. A recent routing architecture is based on Y interconnects, involving the pervasive use of 0°, 60°, and 120° oriented global and semi-global wirings. Unlike the X-routing, Y-routing is observed to support regular routing grid, which is important for simplifying manufacturing processes as well as for routing and design rule checking algorithms. In this paper, we propose a novel Y-routing algorithm that can solve reasonably sized problems in nominal time. Moreover, it can be easily extended for routing with any uniform orientation. Experimental results are quite encouraging and far better than the previously existing solution.
  • Keywords
    VLSI; delays; integrated circuit interconnections; integrated circuit layout; network routing; trees (mathematics); DSM regime; M-routing architectures; Manhattan routing architectures; Y-architecture inteconnect; Y-routing algorithm; cost-effective global routing trees construction; deep submicron regime; design rule checking algorithms; diagonal X architectures; hexagonal minimum Steiner tree construction; interconnect centric VLSI layout design; interconnect delay reduction; manufacturing processes; nonManhattan routing; regular routing grid; semiglobal wirings; Algorithm design and analysis; Asia; Routing; Solid modeling; Steiner trees; Very large scale integration; Wires; Hexagonal MST; Minimum Steiner Tree; Non Manhattan Routing; VLSI Layout Design; Y Routing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microelectronics and Electronics (PrimeAsia), 2012 Asia Pacific Conference on Postgraduate Research in
  • Conference_Location
    Hyderabad
  • ISSN
    2159-2144
  • Print_ISBN
    978-1-4673-5065-5
  • Type

    conf

  • DOI
    10.1109/PrimeAsia.2012.6458646
  • Filename
    6458646