Scaling in floating-gate non-volatile memory technologies and its implication on reliability

In recent years, flash memory has become the driving force in process technology development. This paper discusses a few reliability related effects associated with the scaling of floating-gate based NVM technologies: A) scaling the active area would cause a wider spread of natural Vt of the cells, this brings new challenges in media management and error correction, especially for multi-level applications. B) cell coupling-ratio will reduce due to increasing influence of parasitic capacitances; the inter-cell coupling effect will increase among the neighboring cells; this can affect the cell Vt window or imposes a higher requirement for on chip high voltage handling. C) In embedded memories, a very limited additional thermal budget is allowed on the advanced core logic technology, this brings a new challenge to minimize the thermal budget related to the flash process steps without affecting the flash reliability.