DocumentCode
3296039
Title
Jitter analysis of a PLL-based CDR with a bang-bang phase detector
Author
Ramezani, Mehrdad ; Andre, C. ; Salama, T.
Author_Institution
Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
Volume
3
fYear
2002
fDate
4-7 Aug. 2002
Abstract
This paper provides a timing model to analyze the jitter generation of a bang-bang phase detector for PLL-based clock and data recovery (CDR) applications. Such a CDR is needed in the implementation of the serial data receiver in a broadband transceiver system. The input data is in Non-Return to Zero (NRZ) format. SPICE simulations are used to validate the analysis with particular emphasis on jitter generation caused by the bang-bang phase detector parameters.
Keywords
CMOS digital integrated circuits; data communication equipment; phase detectors; phase locked loops; synchronisation; timing jitter; transceivers; NRZ format; PLL-based CDR; bang-bang phase detector; broadband transceiver system; clock recovery; data recovery; jitter analysis; jitter generation; nonreturn to zero format; serial data receiver; timing model; Analytical models; Clocks; Filters; Phase detection; Phase frequency detector; Phase locked loops; Timing jitter; Transceivers; Voltage control; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on
Print_ISBN
0-7803-7523-8
Type
conf
DOI
10.1109/MWSCAS.2002.1187056
Filename
1187056
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