Asynchronous 8-bit pipelined ADC for self-triggered sensor based applications

This paper presents a novel architecture of Asynchronous Pipelined Analog to digital converter with emphasis on elimination of external clock for integrated self-triggered sensor based applications. The main innovative feature of the proposed pipelined ADC is that it operates without any external clock signal and performs conversion of the analog input like a combinational logic. Complete digital conversion is obtained by asynchronously propagating the partial conversions and the residues through the various stages. The only requirement for the ADC is an external trigger signal from the sensors. The proposed 8 bit ADC implemented in UMC 0.18um CMOS technology has a sampling rate of 5 MHz, with power dissipation of 30 mW and has an active area of 1.0506 mm².