DocumentCode :
3296097
Title :
A high speed and area efficient Booth recoded Wallace tree multiplier for fast arithmetic circuits
Author :
Rao, M.J. ; Dubey, Souvik
Author_Institution :
Centre for VLSI Design, Padmasri Dr. B. V. Raju Inst. of Technol., Narsapur, India
fYear :
2012
fDate :
5-7 Dec. 2012
Firstpage :
220
Lastpage :
223
Abstract :
A Wallace tree multiplier using Booth Recoder is proposed in this paper. It is an improved version of tree based Wallace tree multiplier architecture. This paper aims at additional reduction of latency and area of the Wallace tree multiplier. This is accomplished by the use of Booth algorithm and compressor adders. The coding is done in Verilog HDL and synthesized for Xilinx Virtex 6 FPGA device. The result shows that the proposed architecture is around 67 percent faster than the existing Wallace-tree multiplier, 53 percent faster than the Vedic multiplier, 22 percent faster than the radix-8 Booth multiplier, 18 percent faster than the radix-16 Booth Multiplier. In terms of area also, the proposed multiplier is much efficient.
Keywords :
adders; digital arithmetic; field programmable gate arrays; hardware description languages; Booth recoder; Vedic multiplier; Verilog HDL; Xilinx Virtex 6 FPGA device; compressor adders; fast arithmetic circuits; radix-16 Booth multiplier; radix-8 Booth multiplier; tree based Wallace tree multiplier architecture; Adders; Asia; Computer architecture; Delay; Equations; Field programmable gate arrays; Signal processing algorithms; Arithmetic; Booth Encoder; Compressors; Radix-8; Wallace-Tree;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microelectronics and Electronics (PrimeAsia), 2012 Asia Pacific Conference on Postgraduate Research in
Conference_Location :
Hyderabad
ISSN :
2159-2144
Print_ISBN :
978-1-4673-5065-5
Type :
conf
DOI :
10.1109/PrimeAsia.2012.6458658
Filename :
6458658
Link To Document :
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