Characterization of hot carrier degradation in n-type poly-Si TFTs under dynamic drain pulse Stress with DC gate bias

Degradation of n-type poly-Si TFTs under drain pulse stress is investigated. It is first found that under fixed drain pulse stress on-state current degradation is gradually enhanced with DC gate bias varying from positive value to negative value. Moreover, for positive gate biases, two-stage degradation is observed. A correlation between on-state and off-state degradation is observed. Based on experimental and simulation results, the non-equilibrium PN junction degradation model is discussed and developed.